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Microsoft Specific
Used to perform an atomic bitwise AND operation on a variable shared by multiple threads.
long _InterlockedAnd(
long volatile * value,
long mask
);
long _InterlockedAnd_acq(
long volatile * value,
long mask
);
long _InterlockedAnd_HLEAcquire(
long volatile * value,
long mask
);
long _InterlockedAnd_HLERelease(
long volatile * value,
long mask
);
long _InterlockedAnd_nf(
long volatile * value,
long mask
);
long _InterlockedAnd_np(
long volatile * value,
long mask
);
long _InterlockedAnd_rel(
long volatile * value,
long mask
);
char _InterlockedAnd8(
char volatile * value,
char mask
);
char _InterlockedAnd8_acq(
char volatile * value,
char mask
);
char _InterlockedAnd8_nf(
char volatile * value,
char mask
);
char _InterlockedAnd8_np(
char volatile * value,
char mask
);
char _InterlockedAnd8_rel(
char volatile * value,
char mask
);
short _InterlockedAnd16(
short volatile * value,
short mask
);
short _InterlockedAnd16_acq(
short volatile * value,
short mask
);
short _InterlockedAnd16_nf(
short volatile * value,
short mask
);
short _InterlockedAnd16_np(
short volatile * value,
short mask
);
short _InterlockedAnd16_rel(
short volatile * value,
short mask
);
__int64 _InterlockedAnd64(
__int64 volatile* value,
__int64 mask
);
__int64 _InterlockedAnd64_acq(
__int64 volatile* value,
__int64 mask
);
__int64 _InterlockedAnd64_HLEAcquire(
__int64 volatile* value,
__int64 mask
);
__int64 _InterlockedAnd64_HLERelease(
__int64 volatile* value,
__int64 mask
);
__int64 _InterlockedAnd64_nf(
__int64 volatile* value,
__int64 mask
);
__int64 _InterlockedAnd64_np(
__int64 volatile* value,
__int64 mask
);
__int64 _InterlockedAnd64_rel(
__int64 volatile* value,
__int64 mask
);
Parameters
[in, out] value
A pointer to the first operand, to be replaced by the result.[in] mask
The second operand.
Return Value
The original value of the first operand.
Requirements
Intrinsic |
Architecture |
Header |
|---|---|---|
_InterlockedAnd, _InterlockedAnd8, _InterlockedAnd16, _InterlockedAnd64 |
x86, ARM, x64 |
<intrin.h> |
_InterlockedAnd_acq, _InterlockedAnd_nf, _InterlockedAnd_rel, _InterlockedAnd8_acq, _InterlockedAnd8_nf, _InterlockedAnd8_rel, _InterlockedAnd16_acq, _InterlockedAnd16_nf, _InterlockedAnd16_rel, _InterlockedAnd64_acq, _InterlockedAnd64_nf, _InterlockedAnd64_rel |
ARM |
<intrin.h> |
_InterlockedAnd_np, _InterlockedAnd8_np, _InterlockedAnd16_np, _InterlockedAnd64_np |
x64 |
<intrin.h> |
_InterlockedAnd_HLEAcquire, _InterlockedAnd_HLERelease, _InterlockedAnd64_HLEAcquire, _InterlockedAnd64_HLERelease |
x86, x64 |
<immintrin.h> |
Remarks
The number in the name of each function specifies the bit size of the arguments.
On ARM platforms, use the intrinsics with _acq and _rel suffixes for acquire and release semantics, such as at the beginning and end of a critical section. The intrinsics with an _nf ("no fence") suffix do not act as a memory barrier.
The intrinsics with an _np ("no prefetch") suffix prevent a possible prefetch operation from being inserted by the compiler.
On Intel platforms that support Hardware Lock Elision (HLE) instructions, the intrinsics with _HLEAcquire and _HLERelease suffixes include a hint to the processor that can accelerate performance by eliminating a lock write step in hardware. If these intrinsics are called on platforms that do not support HLE, the hint is ignored.
Example
// InterlockedAnd.cpp
// Compile with: /Oi
#include <stdio.h>
#include <intrin.h>
#pragma intrinsic(_InterlockedAnd)
int main()
{
long data1 = 0xFF00FF00;
long data2 = 0x00FFFF00;
long retval;
retval = _InterlockedAnd(&data1, data2);
printf_s("0x%x 0x%x 0x%x", data1, data2, retval);
}
0xff00 0xffff00 0xff00ff00