Note
Access to this page requires authorization. You can try signing in or changing directories.
Access to this page requires authorization. You can try changing directories.
Microsoft Specific
The operation intrinsics listed in the following table are followed by a description of each intrinsic.
SSE intrinsics use the __m128, __m128i, and __m128d data types, which are not supported on Itanium Processor Family (IPF) processors. Any SSE intrinsics that use the __m64 data type are not supported on x64 processors.
The header file xmmintrin.h contains the declarations for the SSE intrinsics.
Memory and Initialization Store Operations
Intrinsic name |
Operation |
Corresponding instruction |
|---|---|---|
Stores the low value |
MOVSS |
|
Stores the low value across all four words |
MOVSS + Shuffling |
|
Stores four values, address aligned |
MOVAPS |
|
Stores four values, address unaligned |
MOVUPS |
|
Stores four values, in reverse order |
MOVAPS + Shuffling |
|
Sets the low word, and passes in three high values |
MOVSS |
For an explanation of the syntax used in code samples in this topic, see Floating-Point Intrinsics Using Streaming SIMD Extensions.